Google simulated a tenfold cut in qubit overhead. No chip has run it

Google Quantum AI and Google DeepMind split a simulated chip into small flat modules wired together at their edges, building a new family of error-correcting codes on a hyperbolic surface. Circuit-level simulations, not hardware, show the qubit overhead dropping about tenfold at a demanding target error rate, with a further, unbuilt design projected past thirtyfold.

Research desk Google Quantum AI and Google DeepMind, arXiv preprint Read on 2 October 2026

A diagram of small square modules of qubits tiled with sparse connecting lines between their edges, next to a bar chart comparing physical qubits needed per logical qubit: about 95 for the simulated 120-module hyperbolic code, about 36 for the larger projected design, 48 for the published bivariate bicycle code, and over 1,000 for a surface code at the same distance. — The module drawing is a simplified schematic. The bar chart uses the paper's own simulated and projected overhead numbers (Table M3 and the main text); the surface-code comparison is the paper's own claim, not independently checked by us.

The other cost of error correction: how many qubits per qubit

The previous note on this desk is about a code getting more reliable as it grows. This one is about a different number: how many physical qubits it takes to protect one logical qubit at all. The standard answer, the surface code, is popular because its wiring is simple, a flat grid of nearest-neighbor connections, but it is expensive: reaching the error rates a useful computation needs can call for over a thousand physical qubits per logical qubit. Other code families need far fewer qubits in principle, but only by wiring qubits that are physically far apart directly to each other, which is hard to build on a chip.

What the paper reports

On 2 October 2026, fourteen researchers at Google Quantum AI and Google DeepMind posted Low-Overhead Quantum Error Correction with Boundary-Connected Planar Modules to arXiv (2610.03682). We read the preprint in full.

Their idea is to keep the easy part of the surface code, a flat, local grid, but build it in small tiles, called modules, of around 100 qubits each, and connect the edges of those tiles with a sparse set of fixed, non-local links. Chosen correctly, that wiring pattern realizes a code living on a hyperbolic surface, a geometry where these codes can store many more logical qubits per physical qubit than a flat surface allows. Every gate inside a module stays local; only a few links at the boundary go anywhere else.

In circuit-level simulation, not on a chip, a layout of 120 modules of 116 qubits each (13,920 physical qubits in total) held 146 logical qubits at a logical error rate of about 1 in 10 billion per round, using a noise model with ordinary gate errors (0.1%) and the connecting links ten times noisier still (1%). That took about 95 physical qubits per logical qubit, against the paper's estimate of what a surface code would need at the same error rate and code distance: over 1,000. The paper calls this roughly a tenfold saving. Projecting the same idea to a larger, as-yet-unbuilt code, the authors estimate 36 physical qubits per logical qubit at a comparable distance, fewer than the 48 needed by a previously published high-rate code (the "two-gross bivariate bicycle code"), and over thirty times fewer than a surface code at that distance. The paper also designs circuits for running logic gates by physically permuting the modules according to the symmetry of the tiling, and a shared measurement system about 4.5 times smaller than the code itself.

In plain words

A flat sheet of paper can only be folded into shapes with limited room inside; curve that same paper the right way and you can fit more inside the same boundary. The surface code is the flat sheet: simple to build, but it needs a lot of material for a given amount of protected information. This paper curves the sheet, but only on a classical model of the sheet. No one has cut and folded the real paper yet.

What this does not show

Nothing ran on a quantum computer. Every number above is from a circuit-level simulation on an ordinary computer, using an assumed noise model, not a measurement on real hardware.
The biggest gain is a projection, not the simulated result. The tenfold figure is from the simulated 120-module layout; the thirtyfold figure is for a larger code the authors describe mathematically but did not simulate at the circuit level.
The connecting links are assumed, not built. The simulation assumes non-local couplers between module edges can be made to work at the stated error rates; the paper cites early hardware demonstrations of similar links approaching, not matching, that performance.
It has not been peer-reviewed. This is an arXiv preprint, posted by the authors, not yet reviewed or published in a journal.
Logic gates are also theory so far. The "walking circuit" method for running logic by permuting modules is a circuit-level design in the paper, not something tested on hardware either.

Why a reader of this site should care

Put next to our note on Quantinuum's hardware result, this paper shows the field's two live fronts at once: one group squeezing more reliability out of qubits that already exist, the other redesigning the wiring to need fewer of them in the first place. Both matter, and neither is close to a computer that does useful work. A simulation is cheap to run and easy to make look good; the test that counts is whether its assumed error rates survive contact with real, imperfect couplers between real chips. Until that happens, the honest shorthand is: promising arithmetic, not yet an experiment.

Sources

We read the sources above ourselves. Where a figure or number is ours, the article says so. If you find a mistake, tell us: a wrong sentence here gets logged like any other.